Circuit for detecting the phase of received signal

ABSTRACT

A received signal phase detecting circuit in provided in which the circuit scale is small. The circuit functions so as to capture a frame synchronizing signal from a demodulated baseband signal, extract a symbol stream during the period of frame synchronizing signal from the demodulated baseband signal through delay circuits ( 41, 42 ) at a timing matching the bit stream of the captured synchronizing signal, rotating the phase of a corresponding symbol extracted from the symbol stream when the big in the bit in the bit stream is logic “0” by 80°, outputting the symbol after the phase rotation and a corresponding symbol extracted from the symbol stream when the bit in the bit stream is logic “1” from a 0°/180° phase rotating circuit ( 43 ), operating the cumulative average of the output from the 0°/180° phase rotating circuit ( 43 ) for a specific period through cumulative averaging circuits ( 45, 46 ), rotating the phase of the outputs therefrom through a 22.5° phase rotating circuit ( 48 ), and determining the phase of the output therefrom by a phase determining circuit ( 49 ).

TECHNICAL FIELD

The present invention relates to a circuit for detecting the phase of areceived signal and more particularly, to a circuit for detecting thephase of a received signal that is used in a receiver that receives adigitally modulated wave transmitted under a plurality of modulationswith respective different C/N ratios that are required and which detectsa phase angle of a received signal.

BACKGROUND ART

In a broadcast receiver that receives a digitally modulated wave appliedwith hierarchical transmission system in which a plurality ofmodulations with respective different C/N ratios that are required, forexample 8PSK modulation, QPSK modulation and BPSK modulation, arecombined in terms of timing and a digitally modulated wave under suchmodulations is repeatedly transmitted in successive frames, framesynchronizing signals are captured from demodulated base band signals(hereinafter referred to as symbol stream as well), a received signalphase rotation angle at the present time point is obtained from a signalpoint arrangement of the captured frame synchronizing signal, and thedemodulated base band signals are subjected to opposite phase rotationbased on the obtained received signal phase rotation angle, therebymaking the demodulated base band signals coincide with the transmittedsignal phase angle so as to be in absolute phase.

A conventional received signal phase detecting circuit, as shown in FIG.1, comprises: a modulating circuit 1; a frame synchronization detectingcircuit 2; and a frame synchronizing signal generator 3; and inaddition, delay circuits 41 and 42 constituting a block for detecting areceived signal phase; a 0°/180° phase rotating circuit 43; cumulativeaveraging circuits 45 and 46; and a received signal phase determiningcircuit 47 that performs phase determination of a received signal underapplication of a conversion table using ROM. The frame synchronizationdetecting circuit 2 and the frame synchronizing signal generator 3correspond to frame synchronizing signal capturing means for capturing aframe synchronizing signal from the demodulated base band signals andthe delay circuits 41 and 42 correspond to extracting means forextracting symbol streams in the period of a frame synchronizing signalfrom the demodulated base band signals at the timing at which the symbolstreams coincide with a bit stream of the synchronizing signal capturedand reproduced by the frame synchronizing signal capturing means.

The conventional received signal phase detecting circuit shown in FIG. 1performs frequency conversion of a received digitally modulated wave toa predetermined intermediate frequency signal, supplies the intermediatefrequency signal subjected to frequency conversion to the demodulatingcircuit 1 so as to demodulate and the demodulating circuit 1 sends out,for example, demodulated base band signals I(8) and Q(8) (hereinafteralso referred to as base band signals I and Q, omitting the figures ineach of the parentheses that indicates the number of bits together withthe parentheses) of 8 bits that are quantized. The demodulated base bandsignals I(8) and Q(8) are also sent out to the frame synchronizationdetecting circuit 2 in order to capture a frame synchronizing signal,for example, that has been BPSK-modulated.

Description will here be made of mapping for each modulation method onthe transmission side using FIGS. 2(a) to (c). FIG. 2(a) shows signalpoint arrangement in a case where 8PSK modulation is used as amodulation method. In the 8PSK modulation method, a digital signal of 3bits (a, b, c) can be transmitted as 1 symbol, wherein combinations ofbits that constitute 1 symbol are (0, 0, 0), (0, 0, 1), to (1, 1, 1),which are totaled in 8 ways. The digital signals each of 3 bits areconverted to signal point arrangements 0 to 7 on the I-Q vector plane onthe transmission side of FIG. 2(a), which conversion is generally calledas 8PSK mapping.

In the example shown in FIG. 2(a), the bit sequence (0, 0, 0) isconverted to a signal point arrangement “0”, a bit sequence (0, 0, 1) toa signal point arrangement “1”, a bit sequence (0, 1, 1) to a signalpoint arrangement “2”, a bit sequence (0, 1, 0) to a signal pointarrangement “3”, a bit sequence (1, 0, 0) to a signal point arrangement“4”, a bit sequence (1, 0, 1) to a signal point arrangement “5”, a bitsequence (1, 1, 1) to a signal point arrangement “6”, and a bit sequence(1, 1, 0) to a signal arrangement “7”.

FIG. 2(b) shows signal point arrangements in a case where QPSKmodulation is used as a modulation method and in the QPSK modulationmethod, a digital signal of 2 bits (d, e) can be transmitted as 1symbol, wherein combinations of bits constituting the symbol are totaledin 4 ways of (0, 0), (0, 1), (1, 0) and (1, 1). In the example of FIG.2(b), for example, a bit sequence (1, 1) is converted to “1”, a bitsequence (0, 1) to “3”, a bit sequence (0, 0) to “5”, and a bit sequence(1, 0) to “7”. It should be noted that a relation between a signal pointarrangement and a arrangement number in each of other modulation methodsis held in the same way as the relation in case of 8PSK modulation as astandard.

FIG. 2(c) shows signal point arrangements in a case where BPSKmodulation is used as a modulation method and in the BPSK modulationmethod, a digital signal (f) of 1 bit is transmitted as 1 symbol.Conversion of the digital signal (f) is such that, for example, (1) isconverted to a signal point arrangement “0” and (0) is converted to asignal point arrangement “4”.

Now, description will be made of a frame synchronizing signal. In thehierarchical transmission system, a frame synchronizing signal istransmitted after being subjected to BPSK modulation with the lowest C/Nratio that is required. When arrangement is such that a bit stream of aframe synchronizing signal constituted of 16 bits is (S0, S1, . . . S14,S15), wherein the bit steam is sequentially sent out from S0, and a bitstream (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0) or a bitsequence (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1), the latter ofwhich is the former sequence whose latter half 8 bits are inverted, arealternately sent out in successive frames. Hereinafter, the symbolstream of a frame synchronizing signal is also referred to as “SYNCPAT”or “nSYNCPA”T, the latter mark of which is the former symbol streamwhose latter half 8 bits are inverted. The symbol streams are convertedwith BPSK mapping shown in FIG. 2(c) on the transmission side to asignal point arrangement “0” or “4” and the converted symbol steam istransmitted.

When it is confirmed by a demodulated base band signal in the framesynchronization detecting circuit 2 that symbol streams of framesynchronizing signals “SYNCPAT” and “nSYNCPAT” that, as described above,are BPSK-mapped are alternately received in a repeating manner inconstant frame intervals, it is judged that frame synchronization isestablished and a frame synchronization pulse is output in each frameperiod.

In a hierarchical transmission system in which normally, a plurality ofmodulation methods with respective different C/N ratios that arerequired are combined in terms of timing and a digitally modulated waveis repeatedly transmitted in successive frames, header data indicatingthe multiple combinations are multiplexed and a header data indicatingthe multiple combinations is extracted in response to a timing signalthat is generated by a frame synchronizing pulse that is output from theframe synchronization detecting circuit 2 after it is judged that theframe Synchronization has been established. As a result, it is after aframe multiple combination is known that processings for differentmodulation types are separately enabled.

In other words, since the demodulating circuit 1 operates as an 8PSKdemodulating circuit by the time when it is judged that framesynchronization has been established, the I and Q axes of the I-Q vectorplane on the reception side are subjected to phase rotation by θ=45°×n,where n is one of integers of n=0 to 7, as compared with those on thetransmission side according to a phase state of a demodulated carrierwave reproduced in a carrier wave reproducing circuit of thedemodulating circuit 1. For example, in a case of a frame synchronizingsignal transmitted after being BPSK-modulated, symbol streams of theframe synchronizing signal that are BPSK-mapped such as to convert a bit“1” and a bit “0” to a signal point arrangement “0” and a signal pointarrangement “4” respectively have 8 demodulated phases of the framesynchronizing signal according to a phase state of a demodulated carrierwave: a case where being arranged at signal point arrangements “0” and“4” same as on the transmission side, a case where being arranged atsignal arrangements “1” and “5” that receive phase rotation by θ=45°relative to the signal point arrangements on the transmission side and acase where being arranged at signal point arrangements “2” and “6” thatreceive phase rotation by θ=90° relative to the signal pointarrangements on the transmission side.

Signals transmitted after being modulated by means of QPSK modulationand 8PSK modulation are affected by phase rotation similar to the caseof PBSK modulation. When a case where the maximum number of phases ofPSK modulation in which a digitally modulated wave is repeatedlytransmitted in successive frames with combinations of bits in terms oftiming is 8, that is a case of 8PSK modulation, is considered, there are8 received signal phases, each of which is shifted by 45° from theadjacent phase state.

A phase rotation angle of a received signal, however, can be obtained bycomparison of a signal point arrangement of a frame synchronizing signalthat is already known on the transmission side with a signal pointarrangement of a frame synchronizing signal received. Description willbelow be made of this method of obtaining the phase rotation angle.

In the demodulating circuit 1 (see FIG. 1), a symbol stream of a framesynchronizing signal demodulated into base band signals is one that isobtained by BPSK-mapping “SYNCPAT” or “nSYNCPAT” constituted of a bit“1” or “0” on the transmission side and it is apparent from therespective signal point arrangements that a phase difference between thesymbols of the bit “1” and “0” is 180°. Therefore, when all of symbolsof the bit “0” included in a symbol stream of a frame synchronizingsignal received are subjected to 180° phase rotation, a streamconstituted of 16 symbols all with the bit “1” is obtained.

The average value of the obtained stream is acquired and the value isadopted as a point arrangement of a received signal for the bit “1”.Now, since a signal point arrangement for the bit “1” of BPSK is “0”, areceived signal phase rotation angle θ is obtained by comparison of thesignal point arrangement of the BSPK bit with the received signal pointarrangement.

Definition is here made in regard to a relation of a received signalphase rotation angle 0 and a phase rotation angle signal RT (3) that isan output of the received signal phase detecting circuit, as indicatedby the following equation (1):

RT(3)=θ/45   (1)

where θ=n×45° and n is one of integers of n=0 to 7.

Further description will be described based on the conventional exampleof FIG. 1. The frame synchronizing signal generator 3 generates a bitstream of a reproduced frame synchronizing signal corresponding to thepatterns “SYNCPAT” or “nSYNCPAT” of a frame synchronizing signal thatthe generator 3 has captured in response to reception of a framesynchronizing pulse output from the frame synchronization detectingcircuit 2 and the bit stream of a reproduced frame synchronizing signalis supplied to the 0°/180° phase rotating circuit 43. The framesynchronizing signal generator 3 generates a frame synchronizing signalsection signal based on the section of a frame synchronizing signalwhich the frame synchronizing signal generator 3 has captured and theframe synchronizing signal section signal is supplied to the delaycircuits 41 and 42.

The delay circuits 41 and 42 that have received the frame synchronizingsignal section signal delays a symbol stream of a frame synchronizingsignal that is multiplexed into base band signals so that the symbolstream of a frame synchronizing signal that is multiplexed into the baseband signals demodulated by the demodulating circuit 1 and a bit streamof a reproduced frame synchronizing signal sent out from the framesynchronizing signal generator 3 coincide with each other in the timingat the input end position of the 0°/180° phase rotating circuit 43.

Base band signals DI(8) and DQ(8) delayed by the delay circuits 41 and42 are input to the 0°/180° phase rotating circuit 43. The output gatesof the delay circuits 41 and 42 are opened only during a symbol streamsection of a frame synchronization signal with 16 symbols by a framesynchronization signal section signal output from the framesynchronizing signal generator 3. At the input of the 0°/180° phaserotating circuit 43, a reproduced frame synchronizing signal output fromthe frame synchronizing signal generator 3 and the symbol stream of theframe synchronizing signal are made to be coincide with each other intiming by the delay circuits 41 and 42 as described above.

At this point, in the case of logic “0” based on whether a bit in a bitstream of the reproduced frame synchronizing signal supplied is logic“0” or logic “1”, the 0°/180° phase rotating circuit 43 outputs acorresponding symbol in a symbol stream of a frame synchronizing signalthat is multiplexed into demodulated base band signals that are suppliedthrough the delay circuits 41 and 42 after performing a 180° phaserotation thereof, while in the case of logic “1”, the 0°/180° phaserotating circuit 43 outputs a corresponding symbol in a symbol stream ofa frame synchronizing signal that is multiplexed into demodulated baseband signals that are supplied through the delay circuits 41 and 42without performing any phase rotation thereof.

At the input of the 0°/180° phase rotating circuit 43, a symbol streamof a frame synchronizing signal that is multiplexed into demodulatedbase band signals and a bit stream of a reproduced frame synchronizingsignal sent out from the frame synchronizing signal generator 3 are madeto coincide with each other in timing by the delay circuits 41 and 42.Symbol streams DI(8) and DQ(8) of a frame synchronizing signal that areoutput from the delay circuits 41 and 42 whose output gates are openedby a frame synchronizing signal section signal sent out from the framesynchronizing signal generator 3, in the case where a bit stream of thereproduced frame synchronizing signal is logic “0”, receives 180° phaserotation and are respectively sent out to the cumulative averagingcircuits 45 and 46.

FIG. 3(a) shows signal point arrangements of a frame synchronizingsignal when reception is effected at a received signal phase rotationangle θ=0° (absolute phase) and FIG. 3(b) shows how signal pointarrangements of symbol streams VI(8) and VQ(8) after being converted inthe 0°/180° phase rotating circuit 43 are arranged. The symbol streamsVI(8) and VQ(8) are respectively sent out to the cumulative averagingcircuits 45 and 46, cumulative averaging is performed in a predeterminedsection and symbol streams AVI(8) and AVQ(8) that are summed andaveraged in each predetermined section are output. The cumulativeaveraging is performed on the symbol streams VI(8) and VQ(8) in orderthat a signal point arrangement is obtained in a stable manner even whena minor change in phase and/or a change in amplitude of a received baseband signal occur by deterioration in a C/N ratio in reception.

Received signal points (AVI(8) and AVQ(8)) of a BPSK-mapped signal for abit “1” are obtained in the cumulative averaging circuits 45 and 46.Then, the received signal points AVI(8) and AVQ(8) are input to thereceived signal phase determining circuit 47 and a phase rotation anglesignal RT (3) of three bits corresponding to a phase rotation angledefined by the equation (1) is obtained based on a received signal phasedetermination table shown in FIG. 4. In case of a received signal phaserotation angle θ=0° for example, a phase rotation signal that has beendetermined using the received signal phase determination table withrespect to signal points of AVI(8) and AVQ(8) is “0”. Therefore, a bitsequence (0, 0, 0) is sent out as the phase rotation angle signal RT(3). Further, in a case of a received signal phase rotation angle θ=45°,a phase rotation signal is “1” likewise and therefore, a bit sequence(0, 0, 1) is sent out as the phase rotation angle signal RT(3).

Further, in a broadcast receiver that receives a digitally modulatedwave applied with the hierarchical transmission system in which adigitally modulated wave that is transmitted through a plurality ofmodulation methods with respective different C/N ratios that arerequired which modulation methods are combined in terms of timing isrepeatedly transmitted in successive frames, a phase rotation anglesignal RT(3) is obtained in the received signal phase detecting circuitand demodulated base band signals I(8) and Q(8) are subjected toopposite phase rotation using a phase rotation angle signal RT(3) so asto be in absolute phase.

However, when using the above described conventional received signalphase detecting circuit, if the 0°/180° phase rotating circuit 43 isconstituted of table conversion, a required memory capacity is 128 kbytes (=2¹⁶×16 bits) and further if the received signal phasedetermining circuit 47 is constituted of table conversion, a requiredmemory capacity is 2¹⁶×3 bits. In such a way, the scale of the circuitsare large when the 0°/180° phase rotating circuit 43 and the receivedsignal phase determining circuit 47 are constituted of table conversionand thereby a problem has been arisen because of such a large scale incircuit integration.

DISCLOSURE OF THE INVENTION

It is an object of present invention to provide a received signal phasedetecting circuit whose circuit scale is small.

A received signal phase detecting circuit recited in claim 1 of thepresent invention comprises:

frame synchronizing signal capturing means for capturing a framesynchronizing signal from a demodulated base band signal;

extracting means for extracting a symbol stream in the period of a framesynchronizing signal from a demodulated base band signal at the timingat which the symbol stream coincides with a bit stream of thesynchronizing signal captured and reproduced by the frame synchronizingsignal capturing means; and

a cumulative addition/subtraction averaging circuit to which the symbolstream extracted by the extracting means is input and in which when abit in a bit stream of the reproduced synchronizing signal is logic “1”,a corresponding symbol in the symbol stream extracted by the extractingmeans is added, and when the bit in a bit stream of the reproducedsynchronizing signal is logic “0”, a corresponding symbol in the symbolstream extracted by the extracting means is subtracted and results ofcumulative addition/subtraction are averaged over a predeterminedperiod, wherein a received signal phase is determined based on an outputof the cumulative addition/subtraction averaging circuit.

According to the received signal phase detecting circuit recited inclaim 1 of the present invention, a frame synchronizing signal iscaptured from a demodulated base band signal by the synchronizing signalcapturing means and a symbol stream in the period of a framesynchronizing signal is extracted by the extracting means from ademodulated base band signal at the timing at which the symbol streamcoincides with a bit stream of the synchronizing signal captured by theframe synchronizing signal capturing means. In the cumulativeaddition/subtraction averaging circuit, when a bit in a bit stream ofthe captured synchronizing signal is logic “1”, a corresponding symbolin the symbol stream extracted by the extracting means is added, andwhen the bit in a bit stream of the captured synchronizing signal islogic “0”, a corresponding symbol in the symbol stream extracted by theextracting means is subtracted, and results of cumulativeaddition/subtraction are averaged over a predetermined period. A phaseof the received signal is determined based on an output from thecumulative addition/subtraction circuit.

According to a received signal phase detecting circuit recited in claim1 of the present invention, a 0°/180° phase rotating circuit and acumulative averaging circuit that have been conventionally used arereplaced by a cumulative addition/subtraction averaging circuit and the0°/180° phase rotating circuit is unnecessary, thereby reducing acircuit scale.

A received signal phase detecting circuit recited in claim 2 of thepresent invention comprises:

frame synchronizing signal capturing means for capturing a framesynchronizing signal from a demodulated base band signal;

extracting means for extracting a symbol stream in the period of a framesynchronizing signal from a demodulated base band signal at the timingat which the symbol stream coincides with a bit stream of thesynchronizing signal captured and reproduced by the frame synchronizingsignal capturing means;

0°/180° phase rotating means to which the symbol stream extracted by theextracting means is input, for outputting a corresponding symbol of thesymbol stream extracted by the extracting means after performing 180°phase rotation on the corresponding symbol when a bit of a bit stream ofthe reproduced synchronizing signal is logic “0”, and outputting acorresponding symbol of the symbol stream extracted by the extractingmeans after performing no phase rotation on the corresponding symbolwhen the bit of a bit stream of the reproduced synchronizing signal islogic “1”;

a cumulative averaging circuit for summing outputs from the 0°/180°phase rotating means over a predetermined period;

a phase rotating circuit for performing phase rotation of an output fromthe cumulative averaging circuit by (22.5°+45°×n), where n is an integerselected from n =0 to 7; and

a phase determining circuit for determining a phase of an output fromthe phase rotating circuit.

According to the received signal phase detecting circuit recited inclaim 2 of the present invention, a frame synchronizing signal iscaptured from a demodulated base band signal by the synchronizing signalcapturing means and a symbol stream in the period of a framesynchronizing signal is extracted from a demodulated base band signal bythe extracting means at the timing at which the symbol stream coincideswith a bit stream of the synchronizing signal captured by the framesynchronizing signal capturing means. With the bit stream extracted bythe extracting means being received, a corresponding bit of the symbolstream extracted by the extracting means receives 180° phase rotationwhen a bit of the captured synchronizing signal is logic “0” and isoutput from the 0°/180° phase rotating means, and a corresponding symbolof the symbol stream extracted by the extracting means receives no phaserotation when the bit of the bit stream of the captured synchronizingsignal is logic “1” and is output from the 0°/180° phase rotating means.Outputs from the 0°/180° phase rotating means are subjected tocumulative averaging over a predetermined period in the cumulativeaveraging circuit and are output therefrom, an output from thecumulative averaging circuit receives a phase rotation of (22.5°+45°×n),wherein n is an integer selected from n=0 to 7, in the phase rotatingcircuit and a phase of an output of the phase rotating circuit isdetermined by the phase determining circuit.

In this case, since a conventional received signal phase determiningcircuit that has table conversion using ROM is replaced with 0°/180°phase rotating means configured by a multiplier and an adder, and aphase determining circuit of a simple configuration, a circuit scale isreduced.

A received signal phase detecting circuit recited in claim 3 of thepresent invention comprises:

frame synchronizing signal capturing means for capturing a framesynchronizing signal from a demodulated base band signal;

extracting means for extracting a symbol stream in the period of a framesynchronizing signal from a demodulated base band signal at the timingat which the symbol stream coincides with a bit stream of asynchronizing signal captured and reproduced by the frame synchronizingsignal capturing means;

a cumulative addition/subtraction averaging circuit to which the symbolstream extracted by the extracting means is input and in which when abit in a bit stream of the reproduced synchronizing signal is logic “1”,a corresponding symbol in the symbol stream extracted by the extractingmeans is added, and when the bit in a bit stream of the reproducedsynchronizing signal is logic “0”, a corresponding symbol in the symbolstream extracted by the extracting means is subtracted and results ofcumulative addition/subtraction are averaged over a predeterminedperiod;

a phase rotating circuit for performing phase rotation of an output fromthe cumulative addition/subtraction averaging circuit by (22.5°+45°×n),where n is an integer selected from n=0 to 7; and

a phase determining circuit for determining a phase of an output fromthe phase rotating circuit.

According to the received signal phase detecting circuit recited inclaim 3 of the present invention, a frame synchronizing signal iscaptured from a demodulated base band signal by the synchronizing signalcapturing means and a symbol stream in the period of a framesynchronizing signal is extracted from a demodulated base band signal bythe extracting means at the timing at which the symbol coincides with abit stream of the synchronizing signal captured by the framesynchronizing signal capturing means. In the cumulativeaddition/subtraction averaging circuit, when a bit in a bit stream ofthe captured synchronizing signal is logic “1”, a corresponding symbolin the symbol stream extracted by the extracting means is added, andwhen the bit in a bit stream of the captured synchronizing signal islogic “0”, a corresponding symbol in the symbol stream extracted by theextracting means is subtracted, and results of cumulativeaddition/subtraction are averaged over a predetermined period. An outputfrom the cumulative averaging circuit receives a phase rotation of(22.5°+45°×n), wherein n is an integer selected from n=0 to 7, in thephase rotating circuit and a phase of an output of the phase rotatingcircuit is determined by the phase determining circuit.

According to the received signal phase detecting circuit recited inclaim 3 of the present invention, the 0°/180° phase rotating means andthe cumulative averaging circuit employed in the received signal phasedetecting circuit recited in claim 2 according to the present inventionare replaced with the cumulative addition/subtraction averaging circuitand the 0°/180° phase rotating circuit is unnecessary, thereby reducinga circuit scale.

In the received signal phase detecting circuit recited in claim 3 of thepresent invention, a phase of a received signal may be determined in aphase determining circuit, which is arranged in a stage preceding theextracting means, based on an output of a cumulativeaddition/subtraction averaging circuit.

A received signal phase detecting circuit recited in claim 5 of thepresent invention comprises:

frame synchronizing signal capturing means for capturing a framesynchronizing signal from a demodulated base band signal;

a phase rotating circuit for performing phase rotation of a demodulatedbase band signal by (22.5°+45°×n), where n is an integer selected fromn=0 to 7;

extracting means for extracting a symbol stream in the period of a framesynchronizing signal from a base band signal that is phase-rotated bythe phase rotating circuit at the timing at which the symbol streamcoincides with a bit stream of the synchronizing signal captured andreproduced by the frame synchronizing signal capturing means;

code inverting means to which the symbol stream extracted by theextracting means is input, for inverting a code of a correspondingsymbol in the symbol stream extracted by the extracting means to outputthe corresponding symbol after the inversion only when a bit in a bitstream of the reproduced synchronizing signal is logic “0”;

a phase determining circuit that determines a phase of an output fromthe code inverting means;

a gray code converter that performs gray code conversion of an outputfrom the phase determining circuit;

majority determining means for receiving an output of the gray codeconverter and performing majority determination; and

a binary code converter that performs binary code conversion of anoutput from the majority determining means, wherein

an output from the binary code converter is adopted as a received signalphase rotation angle signal.

According to the received signal phase detecting circuit of the presentinvention, a frame synchronizing signal is captured from a demodulatedbase band signal by the synchronizing signal capturing means, thedemodulated base band signal receives a phase rotation of (22.5°+45°×n),wherein n is an integer selected from n=0 to 7, by the phase rotatingcircuit and a symbol stream in the period of a frame synchronizingsignal is extracted from the base band signal that has received phaserotation by the extracting means at the timing at which the symbolstream coincides with a bit stream of the synchronizing signal capturedby the frame synchronizing signal capturing means. When the bit of a bitstream of the captured synchronizing signal is logic “0”, acorresponding symbol in the symbol stream extracted by the extractingmeans is inverted by the code inverting means, a phase of an output fromthe code inverting means is determined by the phase determining circuit,an output from the phase determining circuit receives code conversion toa gray code by the gray code converter, majority determination isperformed on an output from the gray code converter by the majoritydetermining means, which receives the output from the gray codeconverter, an output from the majority determining means receives codeconversion by the binary code converter, and a phase rotation angle of areceived signal is eventually determined based on an output from thebinary code converter.

According to a received signal phase detecting circuit of the presentinvention, a 0°/180° phase rotating circuit and a cumulative averagingcircuit that have conventionally used are replaced with the 22.5° phaserotating circuit and code inverting means and the 0°/180° phase rotatingcircuit and the cumulative averaging circuit are unnecessary, therebyreducing a circuit scale.

In addition, according to a received signal phase detecting circuit ofthe present invention, since a circuit scale can be reduced by usingmajority determining circuits and two phase determination valuesadjacent to each other are different from each other is limited to onebit by gray-coding, therefore even in a case where there arise a minutechange in phase and a change in amplitude of a received base band signaldue to deterioration in a C/N ratio in reception, which has in turnentailed a false phase determination, an influence thereof can beminimized and reliability can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a prior art block diagram showing a configuration of aconventional received signal phase detecting circuit;

FIG. 2(a) to 2(c) are prior art pictorial illustrations of signal pointarrangements used for description of BPSK mapping;

FIG. 3(a) and 3(b) are prior art pictorial illustrations of signal pointarrangements of a frame synchronizing signal after passing a 0°/180°phase rotating circuit in a received signal phase detecting circuit;

FIG. 4 is a prior art pictorial illustration used for description of adetermination table for received signal phase;

FIG. 5 is a block diagram showing configuration of a received signalphase detecting circuit according to an embodiment of the presentinvention;

FIG. 6 is a pictorial illustration used for description of operation ofa received signal phase detecting circuit according to the embodiment ofthe present invention;

FIG. 7 is a table used for description of operation of a received signalphase detecting circuit according to the embodiment of the presentinvention;

FIG. 8 is a block diagram showing configuration of first modification ofa received signal phase detecting circuit according to the embodiment ofthe present invention;

FIG. 9 is a block diagram showing a configuration of second modificationof a received signal phase detecting circuit according to the embodimentof the present invention;

FIG. 10 is a table used for description of operation when a phaserotation angle of a phase rotating circuit in a received signal phasedetecting circuit according to the embodiment of the present invention,is another rotation angle;

FIG. 11 is a block diagram showing configuration of a received signalphase detecting circuit according to a second embodiment of the presentinvention;

FIGS. 12(a) and 12(b) are tables used for description of operations ofgray code conversion and binary code conversion in a received signalphase detecting circuit according to the second embodiment of thepresent invention; and

FIG. 13 is a table used for description of operation of phasedetermination in a received signal phase detecting circuit according tothe second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A description will be made below of a received signal phase detectingcircuit according to the present invention based on an embodimentthereof. FIG. 5 is a block diagram showing a configuration of a receivedsignal phase detecting circuit according to the embodiment of thepresent invention.

A received signal phase detecting circuit according to the embodiment ofthe present invention comprises: a demodulating circuit 1; a framesynchronization detecting circuit 2; a frame synchronizing signalgenerator 3; and in addition to those, delay circuits 41 and 42configuring a block for detection of a received signal phase; a 0°/180°phase rotating circuit 43; cumulative averaging circuits 45 and 46; a22.5° phase rotating circuit 48; and a phase determining circuit 49.

That is, in the received signal phase detecting circuit according to theembodiment of the present invention, outputs AVI(8) and AVQ(8) from thecumulative averaging circuits 45 and 46 are supplied to the 22.5° phaserotating circuit 48 to receive phase rotation; and the phase rotationoutputs RVI(8) and RVQ(8) are supplied to the phase determining circuit49 to obtain a phase rotation angle signal RT(3). Herein, the receivedsignal phase determining circuit 47 with table conversion using a ROM ina conventional example is replaced with the 22.5° phase rotating circuit48 configured by a multiplier, an adder or the like, and a phasedetermining circuit 49 configured by a determining circuit or the like,such as a comparator or the like. The other parts of the configurationare same as the conventional example.

With such a configuration, in the received signal phase detectingcircuit according the embodiment of the present invention, outputsAVI(8) and AVQ(8) from the cumulative averaging circuits 45 and 46 aresupplied to the 22.5° phase rotating circuit 48 and a phase rotation ofan angle 22.5°is performed according to the following equations (2) and(3). It should be noted that operations of the demodulating circuit 1,the frame synchronization detecting circuit 2, a frame synchronizingsignal generator 3, the delay circuits 41 and 42 configuring a block fordetection of a received signal phase, the 0°/180° phase rotating circuit43, and the cumulative averaging circuits 45 and 46 are respectivelysame as those in the conventional case and therefore, descriptionsthereof are omitted.

RVI=AVI cos(22.5°)−AVQ sin(22.5°)  (2)

RVQ=AVI sin(22.5°)+AVQ cos(22.5°)  (3)

Outputs of phase rotation according to the equations (2) and (3) areinput to the phase determining circuit 49; phase rotation angles thereofare determined in the phase determining circuit 49; and a phase rotationangle signal RT(3) is eventually output. A description will be made ofphase rotation and phase determination by the 22.5° phase rotatingcircuit 48 and the phase determining circuit 49 using FIGS. 6 and 7.Conventionally, a received signal phase angle has been determined from(AVI(8) and AVQ(8)) input using threshold angles of φ=22.5°+45°×n,wherein n is an integer selected from n=0 to 7, which is shown in areceived signal phase determination table of FIG. 4, thereby obtaining arotation phase signal RT(3).

However, in the received signal phase detecting circuit according to theembodiment of the present invention, since the outputs (AVI(8) andAVQ(8)) are phase rotated by 22.5°, it may apparently be applied thatφ=22.5°+45°×n, wherein n is an integer selected from n=0 to 7, whilegiving a phase rotation of 22.5° to a threshold angle, which is shown inFIG. 6. As a result, the outputs (RVI and RVQ) of the 22.5° phaserotating circuit 48 are input to the phase determining circuit 49 andthen, it is only required to determine which of phase areas shown inFIG. 6 the inputs (RVI and RVQ) resides in.

Therefore, determination of a received signal phase angle can simply beperformed using the input signals (RVI and RVQ) with a comparator or thelike without using table conversion. Determination of which of 4quadrants on the I-Q vector plane shown in FIG. 6 the received signalphase angle resides in can be obtained from a sign of a signal (RVI andRVQ). Further, in order to perform determination in connection withthreshold angles of 45°×n, where n is an integer selected from n=1, 3,5, 7, at which each quadrant is divided into two, for example,determination on a phase rotation angle signal RT(3)=0 or a phaserotation angle signal RT(3)=1, magnitudes of absolute values of therespective signals (RVI and RVQ) are used for the purpose. Determinationon a phase angle shown in FIG. 6 can be realized using the phasedetermining circuit 49 that performs determination shown in FIG. 7 basedon the above described relations.

According to the procedures as describe above, the received signal phasedetermining circuit 47 conventionally configured so that tableconversion is performed using a ROM is replaced with the 22.5° phaserotating circuit 48 configured by a multiplier and an adder and thephase determining circuit 49 configured by a simple determining circuit,thereby largely reducing a circuit scale when incorporated into anintegrated circuit.

Then, a description will be made of a first modification of the receivedsignal phase detecting circuit according the embodiment of the presentinvention.

In the first modification of the received signal phase detecting circuitaccording to the embodiment of the present invention, as shown in FIG.8, cumulative addition/subtraction averaging circuits 45A and 46Asubstitutes for the 0°/180° phase rotating circuit 43 and the cumulativeaveraging circuits 45 and 46 in the received signal phase detectingcircuit according to the embodiment of the present invention, andoutputs DI(8) and DQ(8) of the delay circuits 41 and 42 are supplied tothe cumulative addition/subtraction averaging circuits 45A and 46A. Whena bit stream of a reproduced frame synchronizing signal output from theframe synchronizing signal generator 3 is logic “1”, correspondingsymbols in symbol streams output from the delay circuits 41 and 42 arerespectively processed in cumulative addition over the section of aflame synchronizing signal section signal; when the bit stream of areproduced frame synchronizing signal output from the framesynchronizing signal generator 3 is logic “0”, corresponding symbols insymbol streams output from the delay circuits 41 and 42 are respectivelyprocessed in cumulative subtraction over the section of a framesynchronizing signal section signal. In the same circuits 45A and 46A,subsequent to the cumulative addition operation or cumulativesubtraction operation, an averaging processing is performed and outputsAVI(8) and AVQ(8) from the cumulative addition/subtraction averagingcircuits 45A and 46A are supplied to the 22.5° phase rotating circuit48.

At this point, when an operation of the 0°/180° phase rotating circuit43 in the received signal phase detecting circuit according to theembodiment of the present invention is considered, 180° phase rotationis equivalent to inversion of a code on each of the respective axes.Therefore, cumulative addition of a received symbol phase-rotated by180° on each axis is equal to cumulative subtraction thereof on eachaxis. Therefore, the 0°/180° phase rotating circuit 43 and thecumulative averaging circuits 45 and 46 can be replaced with thecumulative addition/subtraction averaging circuits 45A and 46A. Thereason why the results of cumulative addition and subtraction receiveaveraging processing is that a signal point arrangement can be obtainedin a stable manner even when a minute change in phase or a change inamplitude of a received base band signal due to deterioration in C/Nratio in reception occurs.

Therefore, if the 0°/180° phase rotating circuit 43 is constituted oftable conversion using ROM, a memory capacity 128 k bytes (=2¹⁶×16 bits)of ROM constituting the 0°/180° phase rotating circuit 43 can be savedand a circuit scale can be further reduced in the first modification ascompared with the case of the received signal phase detecting circuitaccording to the embodiment of the present invention.

Next, a description will be made of a second modification of thereceived signal phase detecting circuit according to the embodiment ofthe present invention.

In the second modification of the received signal phase detectingcircuit according to the embodiment of the present invention, as shownin FIG. 9, phases of demodulated base band signal outputs from thedemodulating circuit 1 receive a phase rotation of 22.5° by the 22.5°phase rotating circuit 48 in the first modification of the receivedsignal phase detecting circuit according to the embodiment of thepresent invention, phase rotation outputs from the 22.5° phase rotatingcircuit 48 are sent out to the delay circuits 41 and 42, outputs fromthe delay circuits 41 and 42 are supplied to the cumulativeaddition/subtraction averaging circuits 45A and 46A and outputs from thecumulative addition/subtraction averaging circuits 45A and 46A are sentout to the phase determining circuit 49. That is, in the secondmodification of the received signal phase detecting circuit according tothe embodiment of the present invention, the 22.5° phase rotatingcircuit 48 in the first modification of the received signal phasedetecting circuit according to the embodiment of the present inventionis shifted to a stage preceding the delay circuits 41 and 42.

In the second modification of the received signal phase detectingcircuit according to the embodiment of the present invention, since theabove described configuration is adopted, outputs RVI(8) and RVQ(8) thatare obtained by performing a phase rotation of 22.5° in the 22.5° phaserotating circuit 48 on outputs from the cumulative addition/subtractionaveraging circuits 45A and 46A in the first modification shown in FIG. 8of the received signal phase detecting circuit according to theembodiment of the present invention are equal to outputs AVI and AVQthat are obtained by performing a cumulative addition/subtractionaveraging operation in the cumulative addition/subtraction averagingcircuits 45A and 46A on 22.5° phase-rotated frame signals that have beenobtained by performing phase rotation of 22.5° on demodulated base bandsignals I(8) and Q(8) in the 22.5° phase rotating circuit 48.

Therefore, the 22.5° phase rotating circuit 48 shown in FIG. 8 may bearranged to be at a stage preceding the delay circuits 41 and 42 withoutany problem as shown in FIG. 9.

There is a case where a circuit that performs 22.5° phase rotation ondemodulated base band signals I(8) and Q(8) is included in thedemodulating circuit 1 of FIG. 9 and in the case, outputs therefrom canbe used, thereby making a configuration of FIG. 9 further simple.

According to the second modification of the received signal phasedetecting circuit according to the embodiment of the present invention,the 0°/180° phase rotating circuit 43 and the cumulative averagingcircuits 45 and 46 that have conventionally been used are replaced withthe cumulative addition/subtraction averaging circuits 45A and 46A.Further, if the 0°/180° phase rotating circuit 43 has table conversionusing ROM, a memory capacity of 128 k bytes (=2^(16×16) bits) can besaved, thereby enabling a circuit scale to be smaller.

It should be noted that in the received signal phase detecting circuitaccording to the embodiment of the present invention and the first andsecond modifications thereof, it is exemplified that determination canbe performed in a simple circuit configuration by using the 22.5° phaserotating circuit 48 instead of table conversion that performsdetermination on an actual received signal phase, while an angle bywhich phase rotation is performed may be not only 22.5° but also thefollowing angles: 67.5°, 112.5°, 157.5°, 202.5°, 247.5°, 292.5° and337.5°.

In the cases, a phase rotation angle signal RT(3) in the received signalphase determining circuit is only required to be changed according to aphase rotation angle that is desired to be implemented. Phase rotationangle signals RT(3) in cases of rotations of the above described 67.5°,112.5°, 157.5°, 202.5°, 247.5°, 292.5° and 337.5° are shown in FIG. 10.FIG. 11 is a block diagram showing configuration of a received signalphase detecting circuit according to a second embodiment of the presentinvention.

A received signal phase detecting circuit according to the secondembodiment of the present invention comprises: a demodulating circuit 1;a frame synchronization detecting circuit 2; and a frame synchronizingsignal generator 3 and in addition, a 22.5° phase rotating circuit 48constituting of a block for detection of a received signal phase ; delaycircuits 41 and 42; a code inverter 59; a phase determining circuit 49;a gray code converter 51; majority determining circuits 52A to 52C; anda binary code converter 53.

That is, in the received signal phase detecting circuit according to thesecond embodiment of the present invention, base band signalsdemodulated in the demodulating circuit 1 are supplied to the framesynchronization detecting circuit 2, a frame synchronizing signal isdetected in the frame synchronization detecting circuit 2 and a framesynchronizing pulse based on the frame synchronizing signal is suppliedto the frame synchronizing signal generator 3. A frame synchronizingsignal period signal and a reproduced frame synchronizing signal arerespectively sent out from the frame synchronizing signal generator 3that have received the frame synchronizing pulse to the delay circuits41 and 42, and the code inverter 59.

On the other hand, base band signals I(8) and Q(8) demodulated in thedemodulating circuit 1 are supplied to the 22.5° phase rotating circuit48 and the signals receive 22.5° phase rotation there. Phase rotationoutputs RI(8) and RQ(8) from the 22.5° phase rotating circuit 48 aresupplied to the delay circuits 41 and 42.

Description will first be made of the 22.5° phase rotation of the baseband signals I(8) and Q(8). The phase rotation in the 22.5° phaserotating circuit 48 is effected according to the following equations (4)and (5):

RI=I cos(22.5°)−Q sin(22.5°)  (4)

RQ=I sin(22.5°)+Q cos(22.5°)  (5)

The delay circuits 41 and 42 that have received a frame synchronizingsignal section signal delay a symbol stream of a frame synchronizingsignal that is multiplexed into base band signals that have received22.5° phase rotation from outputs RI(8) and RQ(8) phase-rotatedaccording to the equations (4) and (5) in the 22.5° phase rotatingcircuit 48 so that the symbol stream of a frame synchronizing signalthat is multiplexed into base band signals, and a bit stream of areproduced frame synchronizing signal that is sent out from the framesynchronizing signal generator 3 coincide with each other in timing atthe input end position of the code inverter 59.

The base band signals DI(8) and DQ(8) that have been delayed by thedelay circuits 41 and 42 are input to the code inverter 59. The outputgates of the delay circuits 41 and 42 are opened only during a symbolstream section of a frame synchronizing signal with 16 symbols by aframe synchronizing signal section signal output from the framesynchronizing signal generator 3. Further, a reproduced framesynchronizing signal output from the frame synchronizing signalgenerator 3 and the symbol stream of the frame synchronizing signal, asdescribed above, are made to coincide with each other in timing by thedelay circuits 41 and 42 at the input of the code inverter 59.

Then, in the code inverter 59, in a case where a bit of the reproducedframe synchronizing signal is logic “0”, the corresponding symbols ofsymbol streams DI(8) and DQ(8) of frame synchronizing signals input tothe code inverter 59 are output after inverted respectively, while in acase where the bit of the reproduced frame synchronizing signal is logic“1”, the corresponding symbols of symbol streams DI(8) and DQ(8) offrame synchronizing signals input to the code inverter 59 are outputunchanged without inversion.

Therefore, while the 0°/180° phase rotating circuit 43 with tableconversion using ROM has conventionally employed, the circuit can bereplaced with the code inverter 59 since an operation of the 0°/180°phase rotating circuit 43 is equal to a code invert operation on each ofthe axes.

Outputs RVI and RVQ from the code inverter 59 are input to the phasedetermining circuit 49 and phase determination is performed usingthreshold angles as shown in FIG. 6. The phase determination in thecircuit is different from the conventional phase determination shown inFIG. 4 and since input signals to be determined have received a 22.5°phase rotation in the 22.5° phase rotating circuit 48 arranged at thepreceding stage, it is apparent that threshold angles, which are usedfor reception phase determination, may also be phase rotated by 22.5°and thereafter set so that the angles φ=45°×n, where n is an integerselected from n=0 to 7. This is shown in FIG. 6. As a result, inputs RVIand RVQ are only required to be determined in the phase determiningcircuit 49 on which of the phase areas shown in FIG. 6 the inputsresides in.

Therefore, similar to the embodiment shown in FIG. 5, the conventionalreceived signal phase determining circuit 47 with table conversion usingROM is replaced with the phase determining circuit 49 comprising the22.5° phase rotating circuit 48 configured by a multiplier and an adderand a simple determining circuit, thereby reducing a circuit scale whenincorporated in an integrated circuit by a great margin.

A phase rotation angle signal RT(3) that is based on a phase rotationangle determined in the phase determining circuit 49 is supplied to thegray code converter 51 to be gray coded according to FIG. 12(a). Bits G0to G2 of a gray coded output are respectively input to the majoritydetermining circuits 52A, 52B and 52C and majority determinations onwhether a bit is “0” or “1” during a predetermined period are performedin the circuits.

Such processings are replacement of cumulative averaging in theconventional example performed on symbol streams VI(8) and VQ(8) whichhave been effected so that signal arrangements can be obtained in astable manner even when there occurs a minute change in phase or achange in amplitude of a received base band signal due to deteriorationin C/N ratio in reception. The outputs G00 to G02 from the majoritydetermining circuits 52A, 52B and 52C are input to the binary codeconverter 53 and inversion of the conversion effected by the gray codeconverter 51 is performed according to FIG. 12(b). An output from thebinary code converter 53 is output as a phase rotation angle signalRT(3).

Each of the majority determining circuits 52A to 52C can be constituted,for example, only of one 4 bit counter if a section for majoritydetermination is a frame synchronizing symbol period, that is 16symbols. For example, when an input signal G0 is input to the enableterminal of a counter and an output QD in the highest place of thecounter is employed as a majority determination output G00, a majorityoutput “1” is obtained if the number of bits “1” in a bit stream G0exceeds 8. However, processing when the numbers of bits “0” and bits “1”are same as each other and other processings are required to beseparately performed but a circuit scale does not become larger due torequirements for such separate processings. In the majority determiningcircuits in the received signal phase detecting circuits according tothe second embodiment of the present invention, since determinationoperations are performed on respective bits of the 3-bit phasedetermination output R(3), three 4-bit counters and peripheral circuitsfor the above described processings are sufficient for the purpose.

The term “section for majority determination” is meant by a set ofsymbols of a frame synchronizing signal. That is, the above descriptionassociated with the term has been such that 16 symbols is a base andmajority determination is performed during a predetermined period.However, according to other thoughts, different ways of processings canbe available: one arbitrary symbol is taken out from the 16 symbols ofeach frame synchronizing signal and such arbitrary symbols are subjectedto majority determinations over several frames (predetermined frames);several arbitrary bits are taken out instead of one arbitrary symboland, likewise, the majority determinations are performed over severalframes (predetermined frames); and in order to delete the code inverter59 shown in FIG. 11, the output gates are opened only when a bit of areproduced frame signal is “1”, and a portion of a bit “0” is discarded.

On the other hand, in the conventional example, the base band signals Iand Q each with 8 bits are necessary to respectively receive cumulativeaddition in 16 times. When sets of 8 bits are summed to performcumulative addition in a total of 16 times, a resulted number amounts to12 bit wide one as the maximum, which requires an adder with 12 bits asthe lowest number of places and at least 12 latch circuits. The set isrequired for each of the base band signals I and Q, thereby increasing acircuit scale.

It is same as in a conventional way that, in signal processings instages after the binary code converter 53, the base band signals I(8)and Q(8) are subjected to opposite phase rotation so as to be inabsolute phase based on a phase rotation angle signal RT(3) signal thatis an output from the binary code converter 53.

In the above description, it is also acceptable that the output R(3) ofthe phase determining circuit is directly input to the majoritydetermining circuits and outputs from the majority determining circuitsare adopted as the phase rotation angle signal RT(3). However, since thedifference in bit between two adjacent phase determination values is 1bit by one time gray-coding, even when a false determination is effectedin phase determination because of a minute change in phase or a changein amplitude of a received base band signal due to deterioration in C/Nratio in reception, an influence thereof can be suppressed to itsminimum. That is, a combination of the gray code converter 51 and themajority determining circuits 52A, 52B and 52C can attain more ofimprovement on reliability of operation.

Further, there is also a case where a circuit in which demodulated baseband signals I(8) and Q(8) are phase-rotated by 22.5° is included in thedemodulating circuit 1 and in this case, outputs from the circuit can beused and the configuration of the received signal phase detectingcircuit according to the second embodiment of the present inventionbecomes simpler.

Further, while the output R(3) from the phase determining circuit 49 areconverted in the gray code converter 51 to G0 to G2, the outputs fromthe phase determining circuit 49 may directly be G0 to G2. Phasedetermination in this case performed by the phase determining circuit 49may be determination shown in FIG. 13.

It should be noted that, while, in the received signal phase detectingcircuit according to the second embodiment of the present invention, itis exemplified that determination by a simple circuit configuration isenabled instead of table conversion in which an actual received signalphase is determined by using the 22.5° phase rotating circuit 48, anglesby which phase rotation is performed may, in that case, be not only22.5° but 67.5°, 112.5°, 157.5°, 202.5°, 247.5°, 292.5° and 337.5°.

In the cases, a phase rotation angle signal R(3) in the phasedetermining circuit 49 is only required to be changed. Phase rotationangle signals R(3) are shown in FIG. 10 for cases where the abovedescribed 67.5°, 112.5°, 157.5°, 202.5°, 247.5°, 292.5° and 337.5° areemployed in phase rotation.

According to the received signal phase detecting circuit according tothe second embodiment of the present invention, the phase determiningcircuit 49 comprising the 22.5° phase rotating circuit 48 configured bya multiplier and an adder and a simple determining circuit aresubstituted for the phase determining circuit with table conversionusing ROM, thereby enabling great reduction in circuit scale when beingincorporated in an integrated circuit.

Further, since the 0°/180° phase rotating circuit 43 which hasconventionally used is replaced with the code inverter 59, when the0°/180° phase rotating circuit 43 has table conversion using ROM, amemory capacity of 128 k bytes (=2¹⁶×16 bits) can be saved. Further, themajority determining circuits 52A to 52C each with a 3-bit width areused instead of the cumulative averaging circuits 45 and 46 each with an8-bit width, which are operated on the respective axes, therebyrealizing great reduction in circuit scale.

ADVANTAGES OF THE INVENTION

As described above, according to a received signal phase detectingcircuit of the present invention, there can be enjoyed effects that acircuit scale can be reduced and a chip area can be effectively used ina case of incorporation of the received signal phase detecting circuitinto an integrated circuit.

What is claimed is:
 1. A received signal phase detecting circuitcomprising: frame synchronizing signal capturing means for capturing aframe synchronizing signal from a demodulated base band signal;extracting means for extracting a symbol stream in a period of a framesynchronizing signal from a demodulated base band signal at a timing atwhich the symbol stream coincides with a bit stream of the synchronizingsignal captured and reproduced by the frame synchronizing signalcapturing means; and a cumulative addition/subtraction averaging circuitto which the symbol stream extracted by the extracting means is inputand in which when a bit in a bit stream of the reproduced synchronizingsignal is logic “1”, a corresponding symbol in the symbol streamextracted by the extracting means is added, and when the bit in a bitstream of the reproduced synchronizing signal is logic “0”, acorresponding symbol in the symbol stream extracted by the extractingmeans is subtracted and results of cumulative addition/subtraction areaveraged over a predetermined period, wherein a received signal phase isdetermined based on an output of the cumulative addition/subtractionaveraging circuit.
 2. A received signal phase detecting circuitcomprising: frame synchronizing signal capturing means for capturing aframe synchronizing signal from a demodulated base band signal;extracting means for extracting a symbol stream in a period of a framesynchronizing signal from a demodulated base band signal at a timing atwhich the symbol stream coincides with a bit stream of the synchronizingsignal captured and reproduced by the frame synchronizing signalcapturing means; 0°/180° phase rotating means to which the symbol streamextracted by the extracting means is input, for outputting acorresponding symbol of the symbol stream extracted by the extractingmeans after performing 180° phase rotation on the corresponding symbolwhen a bit of a bit stream of the reproduced synchronizing signal islogic “0”, and outputting a corresponding symbol of the symbol streamextracted by the extracting means after performing no phase rotation onthe corresponding symbol when the bit of a bit stream of the reproducedsynchronizing signal is logic “1”; a cumulative averaging circuit forsumming outputs from the 0°/180° phase rotating means over apredetermined period; a phase rotating circuit for performing phaserotation of an output from the cumulative averaging circuit by(22.5°+45°×n), where n is an integer selected from n=0 to 7; and a phasedetermining circuit for determining a phase of an output from the phaserotating circuit.
 3. A received signal phase detecting circuitcomprising: frame synchronizing signal capturing means for capturing aframe synchronizing signal from a demodulated base band signal;extracting means for extracting a symbol stream in a period of a framesynchronizing signal from a demodulated base band signal at a timing atwhich the symbol stream coincides with a bit stream of a synchronizingsignal captured and reproduced by the frame synchronizing signalcapturing means; a cumulative addition/subtraction averaging circuit towhich the symbol stream extracted by the extracting means is input andin which when a bit in a bit stream of the reproduced synchronizingsignal is logic “1”, a corresponding symbol in the symbol streamextracted by the extracting means is added, and when the bit in a bitstream of the reproduced synchronizing signal is logic “0”, acorresponding symbol in the symbol stream extracted by the extractingmeans is subtracted and results of cumulative addition/subtraction areaveraged over a predetermined period; a phase rotating circuit forperforming phase rotation of an output from the cumulativeaddition/subtraction averaging circuit by (22.5°+45°×n), where n is aninteger selected from n=0 to 7; and a phase determining circuit fordetermining a phase of an output from the phase rotating circuit.
 4. Areceived signal phase detecting circuit comprising: frame synchronizingsignal capturing means for capturing a frame synchronizing signal from ademodulated base band signal; a phase rotating circuit for performingphase rotation of a demodulated base band signal by (22.5°+45°×n), wheren is an integer selected from n=0 to 7; extracting means for extractinga symbol stream in a period of a frame synchronizing signal from anoutput of the phase rotating circuit at a timing at which the symbolstream coincides with a bit stream of the synchronizing signal capturedand reproduced by the frame synchronizing signal capturing means; acumulative addition/subtraction averaging circuit to which the symbolstream extracted by the extracting means is input and in which when abit in a bit stream of the reproduced synchronizing signal is logic “1”,a corresponding symbol in the symbol stream extracted by the extractingmeans is added, and when the bit in a bit stream of the reproducedsynchronizing signal is logic “0”, a corresponding symbol in the symbolstream extracted by the extracting means is subtracted and results ofcumulative addition/subtraction are averaged over a predeterminedperiod; and a phase determining circuit for determining a phase of anoutput from the cumulative addition/subtraction averaging circuit.
 5. Areceived signal phase detecting circuit comprising: frame synchronizingsignal capturing means for capturing a frame synchronizing signal from ademodulated base band signal; a phase rotating circuit for performingphase rotation of a demodulated base band signal by (22.5°+45°×n), wheren is an integer selected from n=0 to 7; extracting means for extractinga symbol stream in a period of a frame synchronizing signal from a baseband signal that is phase-rotated by the phase rotating circuit at atiming at which the symbol stream coincides with a bit stream of thesynchronizing signal captured and reproduced by the frame synchronizingsignal capturing means; code inverting means to which the symbol streamextracted by the extracting means is input, for inverting a code of acorresponding symbol in the symbol stream extracted by the extractingmeans to output the corresponding symbol after the inversion only when abit in a bit stream of the reproduced synchronizing signal is logic “0”;a phase determining circuit that determines a phase of an output fromthe code inverting circuit; a gray code converter that performs graycode conversion of an output from the phase determining circuit;majority determining means for receiving an output of the gray codeconverter and performing majority determination; and a binary codeconverter that performs binary code conversion of an output from themajority determining means, wherein an output from the binary codeconverter is adopted as a received signal phase rotation angle signal.